8S89831I Datasheet - Renesas

8S89831I, Differential LVPECL-To-LVPECL/ECL Fanout Buffer

Differential LVPECL-To-LVPECL/ECL Fanout Buffer 8S89831I Datasheet Description The 8S89831I is a high speed 1-to-4 Differential- to-LVPECL/ECL Fanou

Features

* Four LVPECL/ECL outputs
* IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
* 50 internal input termination to VT
* Output frequency: >2.1GHz
* Output skew: 30ps (maximum)
* Part-to-part skew: 185ps (maximum)

Applications

* such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fiber Channel.
The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components.
The device also has an

8S89831I-Renesas.pdf