IDT72275 Datasheet - Renesas

IDT72275 CMOS SuperSync FIFO

* Master Reset clears entire FIFO The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In- * Partial Reset clears data, but retains programmable settings * Retransmit operation with fixed, low first word data T R latency time * Empty, Full and Half-Fu.

IDT72275 Features

* Independent Read and Write Clocks (permit reading and writing

* Choose among the following memory organizations: IDT72275

* 32,768 x 18 IDT72285

* 65,536 x 18

* Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs

* 10ns read/write cycle tim

IDT72275 Datasheet (843.27 KB)