IDT72V36100 Datasheet - Renesas

IDT72V36100, 3.3 VOLT HIGH-DENSITY SUPERSYNC FIFO

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO 65,536 x 36 IDT72V36100 131,072 x 36 IDT72V36110 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TI

Features

* Choose among the following memory organizations: IDT72V36100 ⎯ 65,536 x 36 IDT72V36110 ⎯ 131,072 x 36
* Higher density, 2Meg and 4Meg SuperSync II FIFOs
* Up to 166 MHz Operation of the Clocks
* User selectable Asynchronous read and/or write ports (PBGA Only)

Applications

* that need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the state of external control pins Input Width (IW), Output Width (OW), an

IDT72V36100-Renesas.pdf