RL78I1D - MCU

Renesas

Datasheet Details

Ultra-low power consumption technology.
VDD = 1.6 V to 3.6 V.
HALT mode.
STOP mode.
SNOOZE mode RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip oscillator) to ultra-low speed (66.6 s: @ 15 kHz operation with low-speed on-chip oscillator clock).
Multiply/divide/multiply & accumulate instructions are suppo.

📁 RL78I1D Similar Datasheet

Other Datasheets by Renesas

Published: Apr 28, 2016 |