74HC76 Datasheet - STMicroelectronics

74HC76 DUAL J-K FLIP FLOP

The M74HC76 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Depending on with the logic level at J and K inputs, this device changes state on the negative going transition of clock pulse (CK). CLEAR (CLR) and PRESET (PR) are independent of the cloc.

M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED : fMAX = 67MHz (TYP.) at VCC = 6V s LOW POWER DISSIPATION: www.DataSheet4U.comI CC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 76 s DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC76B1R M74HC76M1R .

74HC76 Datasheet (388.70 KB)