74V2T126 Datasheet - STMicroelectronics

74V2T126 DUAL BUS BUFFER

The 74V2T126 is an advanced high-speed CMOS DUAL BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. 3-STATE control input nG has to be set LOW to place the output into the high impedance state. Power down protection is provided on all inputs and outpu.

74V2T126 DUAL BUS BUFFER (3-STATE) HIGH SPEED: tPD = 3.8ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA = 25°C www.DataSheet4U.com s COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) s POWER DOWN PROTECTION ON INPUTS AND OUTPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s IMPROVED LATCH-UP IMMUNITY s s SOT23-8L ORDER CODES PACKAGE SOT23-8L T&R 74V2T126STR .

74V2T126 Datasheet (131.90 KB)