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74VHC126 Datasheet - STMicroelectronics

74VHC126 QUAD BUS BUFFERS

The 74VHC126 is an advanced high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. PIN CONNECTION AND IEC LOGIC SYMBOLS June 1999 1/8 www.DataSheet4U.com 74VHC126 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1, 4, 10, 13 2, 5,.

( DataSheet : www.DataSheet4U.com ) ® 74VHC126 QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA s s s s s s s s s s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 126 IMPROVE.

74VHC126 Datasheet (120.82 KB)