* Super Harvard Architecture Computer (SHARC) 4 Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory, Integrated I/O Peripheral I 2S Support for 8 Simultaneous Receive and T
ADSST-21065LCS-240 Datasheet (409.00 KB)
ADSST-21065LCS-240
409.00 KB
High end/ multichannel/ 32-bit floating-point audio processor.
a
High End, Multichannel, 32-Bit Floating-Point Audio Processor SST-Melody -SHARC
® ®
FUNCTIONAL BLOCK DIAGRAM
SDRAM 128K ؋ 32, BOOT ROM 1M ؋ 8 IRQ G.
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