HC257
70.26kb
Quad 2 channel multiplexer 3-state. The 74VHC257 is an advanced high-speed CMOS QUAD 2 CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-l
TAGS
📁 Related Datasheet
HC2500 - Power Hybrid Circuits
(RCA)
File No. 681 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
D\lCffiLJI]
Solid State Division
Power Hybrid Circuits HC2500
Multi-Purpo.
HC2500 - Multi Purpose Low Distortion 7-Ampere Operational Amplifier
(Harris)
w
w
.D w
t a
S a
e h
U 4 t e
.c
m o
w
w
w
.D
a
S a t
e e h
U 4 t
m o .c
.
HC2500A03 - Hybrid Coupler
(Yantel)
HC2500A03
Hybrid Coupler 3 dB, 90o
Rev B2
Description
The HC2500A03 is a low profile, high performance 3dB hybrid coupler
in a new easy to use, man.
HC2500E03 - Hybrid Coupler
(Yantel)
HC2500E03
Hybrid Coupler 3 dB,Rev9C 0o
Description The HC2100E03 is a low profile, high performance 3dB hybrid coupler in a new easy to use, manufact.
HC2500P03 - Hybrid Coupler
(Yantel)
HC2500P03
Hybrid Coupler 3 dB, 90o
Rev B4
Description The HC2500P03 is a low profile, high performance 3dB hybrid coupler in a new easy to use, manuf.
HC2500S03 - Hybrid Coupler
(Yantel)
HC2500S03
Hybrid Coupler 3 dB, 90o
Rev B0
Description The HC2500S03 is a low profile, high performance 3dB hybrid coupler in a new easy to use, manuf.
HC2500U03-050 - 90 Degree Hybrid
(Yantel)
Data Sheet HC2500U03-050
90 Degree Hybrid
2.30 GHz-2.65 GHz
Key Patents Lead Microwave Tech
Features
● Small Size (2×2mm) ● Very Low Loss ● Tight Am.
HC2500U03-055 - 90 Degree Hybrid
(Yantel)
Data Sheet HC2500U03-055
90 Degree Hybrid
2.30 GHz-2.65 GHz
Key Patents Lead Microwave Tech
Features
● Small Size (2×2mm) ● Very Low Loss ● Tight Am.
HC2509C - Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
(Hynix Semiconductor)
HC2509C
March 1999
HC2509C
Features
l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and .
HC2510 - Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
(Hynix Semiconductor)
HC2510C
HC2510C
Features
l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC10.