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HC2509C Datasheet - Hynix Semiconductor

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2509C Features

* l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs No External RC Network Required External Feedback (

HC2509C General Description

The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The HC2509C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. The propagation delay from the CLK i.

HC2509C Datasheet (84.01 KB)

Preview of HC2509C PDF

Datasheet Details

Part number:

HC2509C

Manufacturer:

Hynix Semiconductor

File Size:

84.01 KB

Description:

Phase-locked loop clock distribution for synchronous dram applications.

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HC2510 Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications (Hynix Semiconductor)

HC2510C Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications (Hynix Semiconductor)

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HC2509C Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Hynix Semiconductor

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