HC2509C Datasheet - Hynix Semiconductor

HC2509C, Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2509C March 1999 HC2509C .
The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.

Applications

* Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Ea

HC2509C_HynixSemiconductor.pdf