HC2510C Datasheet (Hynix Semiconductor) - Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2510C, Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

The HC2510C is a low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.

The HC2510C operates at 3.3V Vcc and provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

The propagation delay from the CLK in

HC2510C Features

* l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to S