HC2510C Datasheet, Applications, Hynix Semiconductor

✔ HC2510C Features

l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2

✔ HC2510C Application

Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input t

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HC2510C

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📄 Datasheet

Description:

Phase-locked loop clock distribution for synchronous dram applications. The HC2510C is a low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. The H

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HC2510C Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Hynix Semiconductor