HCF40105B - FIFO REGISTER
OF ”B” SERIES CMOS DEVICES” READY) indicates if the FIFO contains data.
As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.
EY (Plastic Package) F (Ceramic Package) C1 (Chip Carrier)
HCC40105B HCF40105B FIFO REGISTER .
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INDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS 3-STATE OUTPUTS EXPANDABLE IN EITHER DIRECTION STATUS INDICATORS ON INPUT AND OUTPUT RESET CAPABILITY STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No 13A, ”STANDARD SPEC
HCF40105B Features
* TER RESET (MR) sets all the control logic marker bits to ”0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. 8/12 HCC/HCF40105B Plastic DIP14 MECHANICAL DATA mm M
