* TER RESET (MR) sets all the control logic marker bits to ”0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. 8/12 HCC/HCF40105B Plastic DIP14 MECHANICAL DATA mm M
HCF40105B Datasheet (260.50 KB)
HCF40105B
260.50 KB
Fifo register.
HCC40105B HCF40105B
FIFO REGISTER
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INDEPENDENT ASYNCHRONOUS INPUTS AND OUTPUTS 3-STATE OUTPUTS EXPANDABLE IN EITHER DIRECTION S.
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