STA1295

Automotive infotainment processors

STMicroelectronics

STA1295 Features

* AEC-Q100 qualified Grade 3 Core and infrastructure

* ARM® Single or Dual Core Cortex® A7 up to 650 MHz with NEON instructions and FPU

* Memory organization

* L1 Cache: 32 KB instruction, 32 KB data

* L2 Cache: 256 KB

* 768 KB embedded SRAM

STA1295 General Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Application processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STA1295 Datasheet (2.26 MB)