74LS161
DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature
. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS160A and LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. ), Count Enable Three control inputs
- Parallel Enable (PE Parallel (CEP) and Count Enable Trickle (CET)
- select the mode of operation as shown in the tables below . The Count , and PE inputs are HIGH. Mode is enabled when the CEP , CET , the counters will...
