* Super high dense cell design for low RDS(ON). Rugged and reliable. Suface Mount Package. ESD Protected. G S STU SERIES TO - 252AA( D- PAK ) G DS STD SERIES TO - 251( I - PAK ) ABSOLUTE MAXIMUM RATINGS (TC=25°C unless otherwise noted) Symbol Parameter VDS Drain-Source Voltage VGS Gate-Source Vo
STD601S
SamHop
102.06 KB
P-channel logic level enhancement mode field effect transistor.
Gr Pr
STU/D601S
Sa mHop Microelectronics C orp.
P-Channel Logic Level Enhancement Mode Field Effect Transistor
Ver 1.2
PRODUCT SUMMARY
VDSS
ID R.
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