Description
Pin No 3 1 18 16 4 2 19 17 5 6 7 8 9 10 11 12 Symbol FSX0 FSX1 FSX2 FSX3 FSR0 FSR1 FSR2 FSR3 TSX DC CLKC CS MODE GND BCLK XSYC
TIME SLOT ASSIGNMENT CIRCUIT
Description A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made.A frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made.This pin pulls low during any active transmit time slot
Features
- l l l l l l l l Single, 5V operation Low power consumption: 5mW Controls four 1 CHIP CODEC Independent transmit and receive frame syncs enables channel unidirectional mode Up to 64 time slots per frame Compatible with KT8554/7 CODECs TTL and CMOS compatible.
KT8555J Datasheet
