M368L6423FTN-CB3B0 - DDR SDRAM
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 (for x72 module) Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip
256MB, 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC Revision 1.2 May.
2004 Rev.
1.2 May, 2004 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (August, 2003) - First release Revision 1.1 (August, 2003) - Added K4H560838F based Module.
Revision 1.2 (May, 2004) - Modified IDD current spec.
DDR SDRAM Rev.
1.2 May, 2004 256MB, 512MB Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb F-die (
M368L6423FTN-CB3B0 Features
* Net Wiring Clock Input
* CK0/CK0
* CK1/CK1
* CK2/CK2
* Clock Wiring DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs Notes : 1. DQ-to-I/O
