LV8071LP Datasheet - Sanyo Electric

LV8071LP Piezoelectric Actuator Driver IC

of the Operation * CLK1 and CLK2 inputs CLK1 incorporates the quarter-dividing circuit. To input 39MHz directly, input it directly to the CLK1 pin. When the dividing circuit is provided externally, input 9.75MHz to the CLK2 pin. Short-circuit the unused CLK pin to GND. * 1 cycle: One.

LV8071LP Features

* The actuator using the piezoelectric device is driven by the external CLK input and simple control signal.

* The 39MHz (CLK1 pin input) CLK input is divided into quarters internally to generate the 9.75MHz input. The operation time is generated using this as a base CLK to ensure the output a

LV8071LP_SanyoElectric.pdf