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S-13D1 - HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR

Datasheet Summary

Features

  • 1.0 V to 3.6 V, selectable in 0.05 V step A ceramic capacitor of 0.22 μF or more can be used for the output capacitor.
  • Input voltage: 1.5 V to 5.5 V.
  • High-accuracy output voltage: ±1.0% (1.0 V to 1.45 V output product :±15 mV).
  • Dropout voltage: 80 mV typ. (2.8 V output product, IOUT = 100 mA).
  • Low current consumption: During operation: 39 μA typ. , 58 μA max. (per circuit) During power-off: 0.1 μA typ. , 1.0 μA max. Possible to output 150 mA (at VIN ≥ VOUT(S) +.

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Datasheet Details

Part number S-13D1
Manufacturer Seiko
File Size 687.23 KB
Description HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
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S-13D1 Series www.sii-ic.com © Seiko Instruments Inc., 2012 SUPER-SMALL PACKAGE 2-CIRCUIT BUILT-IN DELAY FUNCTION HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.1.1_00 The S-13D1 Series, developed by using the CMOS technology, is a 2-channel positive voltage regulator IC which has low dropout voltage, high accuracy output voltage and low current consumption. A 0.22 μF small ceramic capacitor can be used, and the S-13D1 Series includes a load current protection circuit that prevents the output current from exceeding the current capacitance of the output transistor and a thermal shutdown circuit that prevents damage due to overheating. Also, C / F type in the S-13D1 Series has a built-in delay function that sets the difference of rising time in a channel. „ Features 1.
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