HYM72V1005GU-50 Datasheet (Siemens) - 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module

HYM72V1005GU-50, 3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module

1M x 64 DRAM module (access time 50 ns) 1M x 64 DRAM module (access time 60 ns) 1M x 72 DRAM module (access time 50 ns) 1M x 72 DRAM module (access time 60 ns) Pin Names A0-A9 DQ0 - DQ63 CB0-CB7 RAS0, RAS2 CAS0 - CAS7 WE0, WE2 OE0, OE2 Vcc Vss SCL SDA SA0-SA2 N.C.

DU Address Input Data Input/Outpu

3.3V 1M × 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module 168pin unbuffered DIMM Module with serial presence detect HYM64V1005GU-50/-60 HYM72V1005GU-50/-60 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications 1 bank 1M x 64, 1M x 72 organisation Optimized for byte-write non-parity or ECC applications Extended Data Out (EDO) Performance: -50 tRAC tCAC tAA tRC tHPC RAS Access Time CAS Access Time Access Time from Address Cycle Tim