* tion time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown. tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD tT + 1.4 V 50 Ohm INPUT 1.4V Z=50 Ohm I/O tAC tLZ tOH tAC 50 pF OUTPUT 1.4V tHZ fig.1 5. If clock rising time is lon
HYS64V8000GU Datasheet (68.84 KB)
HYS64V8000GU
Siemens
68.84 KB
3.3v 8m x 64-bit sdram module 3.3v 8m x 72-bit sdram module.
3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules
HYS64V8000GU-10 HYS72V8000GU-10
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168 Pin JEDEC.
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