HYS72V8000GU-10 Datasheet (Siemens) - 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

HYS72V8000GU-10, 3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

PC66 8M x 64 SDRAM module PC66 8M x 72 SDRAM module Pin Names A0-A11 BA0,BA1 DQ0 - DQ63 CB0-CB7 RAS CAS WE CKE0 CLK0, CLK1 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C.

Address Inputs( RA0 ~ RA11 / CA0 ~ CA8) Bank Selects Data Input/Output Check Bits (x72 organisation only) Row Address Strobe Colum

3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module 168 pin unbuffered DIMM Modules HYS64V8000GU-10 HYS72V8000GU-10 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications 1 bank 8M x 64, 8M x 72 organisation Optimized for byte-write non-parity or ECC applications Fully PC66 layout compatible JEDEC standard Synchronous DRAMs (SDRAM) Performance: -10 fCK tAC Max.

Clock frequency Max.

access time from clock 66 MHz @ CL=2 100 MHz @ C

HYS72V8000GU-10 Features

* tion time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit shown. tCH 2.4 V CLOCK 0.4 V tCL tSETUP tHOLD tT + 1.4 V 50 Ohm INPUT 1.4V Z=50 Ohm I/O tAC tLZ tOH tAC 50 pF OUTPUT 1.4V tHZ fig.1 5. If clock rising time is lon