Description
!iinoOliC!i 82S114 I!I 2048-BIT BIPOLAR ROM (256x8 PROM) 4096-B11 BIPOLAR ROM (512x8 PROM) 82S115 - - - - - - - - - - - - 1 DIGITAL 8000 SERIES TTL.
The 82S 114 and 82S 115 are Schottky-clamped Read Only Memories, incorporating on-chip data output registers.
Features
* ORGANIZATION: 82S114 - 256 X 8 82S115 - 512 X 8
* ADDRESS ACCESS TIME - 60ns, MAXIMUM
* POWER DISSIPATION - 165pW/BIT, TYPICAL
* INPUT LOADING - (-100pA), MAXIMUM
* ON-CHIP ADDRESS DECODING
* ON-CHIP STORAGE LATCHES
* TRI-STATE OUTPUTS
Applications
* MICROPROGRAMMING HARDWIRE ALGORITHMS CHARACTER GENERATION CONTROL STORE SEQUENTIAL CONTROLLERS
PIN CONFIGURATION
IPACKAGE
* 82S114
82S115
* 1 - Ceramic
BLOCK DIAGRAM
AOo-,
* t
ADDRESS LINES
A7o-L
* o-f
ASo
* - -L
* _
