Description
SinootiCS 82S116 256-BIT BIPOLAR RAM (256xl RAM) 82S117 _;=_ .I _ _ _ _ _{_82S_11_6T_RI_-ST_AT_E>_{82_S1_17_0P_EN_CO_LL_EC_TOR *-f} FEBRUARY 19.
The 82S116 and 82S117 are Schottky clamped TTL, read/write memory arrays organ ized as 256 words of one bit each.
Features
* ORGANIZATION - 256 X 1
* ADDRESS ACCESS TIME - 40n5, MAXIMUM
* WRITE CYCLE TIME - 25n5, MAXIMUM
* POWER DISSIPATION - 1.5mW/BIT TYPICAL
* INPUT LOADING - (-100JlA) MAXIMUM
* OUTPUT FOLLOWS COMPLEMENT OF DATA INPUT
DURING WRITE
* ON-CHIP ADDRE
