8051F310 Datasheet (Silicon Laboratories)

8051F310, 8/16 kB ISP Flash MCU

90 8.3.

Interrupt Handler 93 8.3.1.

MCU Interrupt Sources and Vectors 94 8.3.2.

External Interrupts 95 8.3.3.

Interrupt Priorities 95 Rev.

1.7 3 C8051F310/1/2/3/4/5/6/7 8.3.4.

Interrupt Latency 95 8.3.5.

Interrupt Register Descriptions 97 8.4.

Power Management Modes 102 8.4.1.

Idle Mode 1

C8051F310/1/2/3/4/5/6/7 8/16 kB ISP Flash MCU Family Analog Peripherals - 10-Bit ADC (C8051F310/1/2/3/6 only) High Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 200 ksps Up to 21, 17, or 13 external single-ended or differential inputs VREF from external pin or VDD Built-in temperature sensor External conversion start input Programmable hysteresis and response time Configurabl

8051F310 Features

* 28 1.2. On-Chip Memory 29 1.3. On-Chip Debug Circuitry 30 1.4. Programmable Digital I/O and Crossbar 31 1.5. Serial Ports 32 1.6. Programmable Counter Array 32 1.7. 10-Bit Analog to Digital Converter 33 1.8. Comparators 34 2. Absolute Maximum Ratings 35 3. Global DC Electrical Characteristics