Si5323 Datasheet - Silicon Laboratories

Features

* Pin-selectable output frequencies

* Dual clock outputs with selectable ranging from 8 kHz

* 708 MHz signal format (LVPECL, LVDS, CML,

* Ultra-low jitter clock outputs as low CMOS) as 250 fs rms (12 kHz

* 20 MHz)

* Support for ITU G.709 FEC ratios 270 fs rms (50 k