* 4, 8, and 12 Output 100 MHz PCIe Gen1 through Gen 6, compliant clock fanout buffer
* Low additive jitter: 0.02 ps rms max, Gen 6
* Low-power, push-pull, HCSL compatible differential outputs
* 10 MHz to 200 MHz clock input
* Individual hardware control pins
Si53204
Skyworks
1.17 MB
Low power gen 1 to gen 6 clock buffer.
DATA SHEET
Si53212, Si53208, and Si53204: 12/8/4-Output PCI-Express Low Jitter, Low Power Gen 1 to Gen 6 Clock Buffer
Applications
* Data ce.
📁 Related Datasheet
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