Si5383 Datasheet - Silicon Laboratories

Si5383, Network Synchronizer Clocks Supporting

Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs The Si5383/84 combines the industry’s smallest footprint an.
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Features

* One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
* Input frequency range:
* External crystal: 25-54 MHz
* REF clock: 5-250 MHz
* Diff clock: 8 kHz - 750 MHz
* LVCMOS clock: 1 PPS, 8

Applications

* Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
* Telecom Grand Master Clock (T-GM) as defined by ITU-T G.8273.1
* Telecom Boundary Clock and Slave Clock (T-BC, T-TSC) as defined by ITU-T G. 8273.2
* IEEE 1588 (PTP) slave clock synchronization
* S

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