* One or three independent DSPLLs in a single monolithic IC supporting flexible SyncE/IEEE 1588 and SETS architectures
* Input frequency range:
* External crystal: 25-54 MHz
* REF clock: 5-250 MHz
* Diff clock: 8 kHz - 750 MHz
* LVCMOS clock: 1 PPS, 8
Si5384
Silicon Laboratories
892.74 KB
Network synchronizer clocks supporting.
Si5383/84 Rev D Data Sheet Network Synchronizer Clocks Supporting 1 PPS to 750 MHz Inputs The Si5383/84 combines the industry’s smallest footprint an.
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