TC59SM816BFT Datasheet | Toshiba

DESCRIPTION TC59SM816BFT/BFTL is a CMOS synchronous dynamic random access memory organized as 4,194,304-words × 4 banks × 16 bits and TC59SM808BFT/BFTL is organized as 8,388,608 words × 4 banks × 8 bits and The TC59SM804BFT/BFTL is organized as 16,777,216 words × 4 banks × 4 bits. Fully synchronous operations are referenced to the positive edges of clock input and can transfer data up to 143M words per second. These devices are controlled by mands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices are ideal for main memory in applications such as work-stations. FEATURES PARAMETER -70 t CK t AC t RC Clock Cycle Time (min) Access Time from CLK (max) Ref/Active to Ref/Active mand Period (min) 7 ns 40 ns 5.4 ns 56 ns 80 m A 100 m A 3 m A TC59SM816/M808/M804 -75 7.5 ns 45 ns 5.4 ns 65 ns 75 m A 95 m A 3 m A -80 8 ns 48 ns 6 ns 68 ns 70 m A 90 m A 3 m A t RAS Active to Precharge mand Period (min) ICC1 Operation Current (max) (Single bank) ICC4 Burst Operation Current (max) ICC6 Self-Refresh Current (max) - - - - - - - - - - - - - - - Single power supply of 3.3 V ± 0.3 V Up to 143 MHz clock frequency . Synchronous operations: All signals referenced to the positive edges of clock Architecture: Pipeline Organization TC59SM816BFT/BFTL: 4,194,304 words × 4 banks × 16 bits TC59SM808BFT/BFTL: 8,388,608 words × 4 banks × 8 bits TC59SM804BFT/BFTL: 16,777,216 words × 4 banks × 4 bits Programmable Mode register Auto Refresh and Self Refresh Burst Length: 1, 2, 4, 8, Full page CAS Latency: 2, 3 Single Write Mode Burst Stop Function Byte Data Controlled by LDQM, UDQM (TC59SM816) 8K Refresh cycles/64 ms Interface: LVTTL Package TC59SM816BFT/BFTL: TSOPII54-P-400-0.80B TC59SM808BFT/BFTL: TSOPII54-P-400-0.80B TC59SM804BFT/BFTL: TSOPII54-P-400-0...