TC74VHC175FK Overview
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ). The information data applied to the D inputs (D1 thru D4) are transferred to the outputs (Q1 thru Q4 and Q1 thru Q4 ) on the positive-going edge of the clock pulse.
TC74VHC175FK Key Features
- High speed: fmax = 210 MHz (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Power down protection is provided on all inputs
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage range: VCC (opr) = 2 to 5.5 V
- Low noise: VOLP = 0.8 V (max)
- Pin and function patible with 74ALS175