SCB18X128800AF-10E2, SCB18X128800AF-10E Datasheet (UniIC)

SCB18X128800AF-10E2, SCB18X128800AF-10E, 128Mbit DDR OPI Xccela PSRAM

and Clock toggle suggestion; 3.

Figure7 * Figure10, Figure13 correct read DQ preamble and tHZ; 4.

Table21 * Table22 update IDD value; 5.

Remove RBX description; 6.

Add MR8[5] bit description; 7.

Add MR0[6] bit description; 8.

Update MR6 description; 9.

Remove the clock stop recommend

Sept.

2024 SCB18X128XX0AF 128Mbit DDR OPI Xccela PSRAM EU RoHS Compliant Products Data Sheet Rev.

H Data Sheet SCB18X128XX0AF 128Mbit DDR OPI Xccela PSRAM Revision History Date Revision 2022-12-08 A 2023-02-02 B 2023-03-14 C 2023-03-28 D 2023-06-27 E 2023-09-6 F 2024-07-31 G 2024-09-04 H Subjects (major changes since last revision) 1.

P4 IDD spec done 2.

Marketing want Ron 250ohm, based on Bailu, Ron max is 240ohm, need to discuss 1.

Table 6, RL 400MHZ and 333MHZ changed 2.

SCB18X128800AF-10E2 Features

* 8. Update tCPH & tDQSCK 9. Update tSP/tHD of Table 24 10. Update tDS/tDH of Table 25 11. Remove Standby and Half Sleep Current @125C of Table 22 12. Remove Half Sleep Current @105C of Table 22 13. Remove Standby Current @85C of Table 22 14. Update tKHKL @300Mhz/333Mhz/400Mhz of Table 24 15. Add tHP/