VG4616321B Datasheet - Vanguard International Semiconductor

VG4616321B CMOS Synchronous Graphic RAM

Table 1. Pin Description of VG4616321 Type Description Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and control the output registers. Input Clock Enable: CKE activates(HIGH) and deact.

VIS Overview Preliminary VG4616321B/VG4616322B 262,144x32x2-Bit CMOS Synchronous Graphic RAM The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by 256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start.

VG4616321B Features

* the write per bit and the masked block write functions. By having a programmable Mode register and special mode register, the system can choose the best suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, and when combined with

VG4616321B Datasheet (1.35 MB)