Description
Preliminary
VG4632321A 524,288x32x2-Bit CMOS Synchronous Graphic RAM
Table 1 shows the details for pin number, symbol, type, and description.Table 1. Pin Description of VG4632321A
Input Clock: CLK is driven by the system clock.All SGRAM input signals are sampled on the positive edge of CLK.CLK also increments the internal burst counter and control the output registers.Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.If CKE goes low synchronously with clock (s
Features
- the write per bit and the masked block write functions. By having a programmable Mode register and special mode register, the system can choose the best suitable modes to maximize its performance. These devices are well suited for.
VG4632321A_VanguardInternationalSemiconductor.pdf
