* include cyclic replay of frames at a user definable rate - either built by the external CPU directly inside the FIFOs or captures from incoming traffic. A dual MII Management interface sets up and controls the PHYs. Frames are monitored, and the statistics generated can be analyzed at a later time.
VSC7321
Vitesse Semiconductor
611.67 KB
10 x 1 gigabit ethernet mac.
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PHYSICAL LAYER PRODUCT ETHERNET PRODUCT
VSC7321
VSC7321 Meigs-II™ - 10 x 1G and 10G Ethernet MAC Chip
S P E C I F I C AT I O N S .
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