* 1 PIN CONFIGURATION 1 3.1 4.1 4.2 5. 5.1 5.2 6. 6.1 6.2 6.3 6.4 7. 7.1 7.2 7.3 8. 9. 10. Block diagram 2 Clock Outputs 3 Power Pins 3 RESERVED 4 Register 5 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH) 4 Register 6 : Output Control ( 1 = Active, 0 = Inactive ) (Default =FFH) 4 Blo
W83176G-735 Datasheet (271.01 KB)
W83176G-735
Winbond
271.01 KB
(w83176x-735) dimm ddr zero delay buffer.
www.DataSheet4U.com
W83176R-735 W83176G-735 Winbond 3 DIMM DDR ZERO DELAY BUFFER
Date:
Mar/31/2006
Revision:
1.1
W83176R-735/W83176G-735
3 DIMM .
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