* 1 PIN CONFIGURATION 1 BLOCK DIAGRAM 2 PIN DESCRIPTION 3 5.1 5.2 6. 7. Clock Function Pins3 Control Signal Pins3 POWER PINS 4 I2C CONTROL AND STATUS REGISTERS 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 Register 0 ~ Register 5 RESERVED4 Register 6: Output Control (1 = Enable, 0 = Disab
W83176G-733 Datasheet (313.13 KB)
W83176G-733
Winbond
313.13 KB
(w83176x-733) winbond dual bank ddr buffer.
www.DataSheet4U.com
W83176R-733 W83176G-733
Winbond Dual Bank DDR BUFFER For VIA CHIPSET
Date: Mar/22/2006
Revision:
1.0
W83176R-733/W83176G-733
.
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