17S15APC Datasheet (Xilinx) - Spartan-II/Spartan-IIE Family OTP Configuration PROMs

17S15APC, Spartan-II/Spartan-IIE Family OTP Configuration PROMs

Pins not listed are "no connects." Table 1: XC17S00A PROM Pinouts 8-pin PDIP (PD8) and VOIC/TSOP (VO8) 1 Pin Name DATA 20-pin SOIC (SO20) 1 44-pin VQFP (VQ44) 40 Pin Description Data output, High-Z state when either CE or OE are inactive.

During programming, the DATA pin is I/O.

Note that OE can

17S15APC Features

* Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices

* Simple interface to the Spartan device

* Programmable reset polarity (active High or active Low)

* Low-power CMOS floating gate proc