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17S30A

Spartan-II/Spartan-IIE Family OTP Configuration PROMs

17S30A Features

* Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices

* Simple interface to the Spartan device

* Programmable reset polarity (active High or active Low)

* Low-power CMOS floating gate proc

17S30A General Description

Pins not listed are "no connects." Table 1: XC17S00A PROM Pinouts 8-pin PDIP (PD8) and VOIC/TSOP (VO8) 1 Pin Name DATA 20-pin SOIC (SO20) 1 44-pin VQFP (VQ44) 40 Pin Description Data output, High-Z state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can.

17S30A Datasheet (129.65 KB)

Preview of 17S30A PDF

Datasheet Details

Part number:

17S30A

Manufacturer:

Xilinx

File Size:

129.65 KB

Description:

Spartan-ii/spartan-iie family otp configuration proms.

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17S30A Spartan-II Spartan-IIE Family OTP Configuration PROMs Xilinx

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