Description
Description
The XCR3032XL is a 3.3V, 32-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions.A total of two function blocks provide 750 usable gates.Pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 MHz.TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique.Xilinx employs a cascade of CMOS gates to implement its sum of products instead o
Features
- Lowest power 32 macrocell CPLD 5.0 ns pin-to-pin logic delays System frequencies up to 200 MHz 32 macrocells with 750 usable gates Available in small footprint packages - 48-ball CS BGA (36 user I/O pins) - 44-pin VQFP (36 user I/O) - 44-pin PLCC (36 user I/O) Optimized for 3.3V systems - Ultra-low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power™ (FZP) CMOS desi.