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XCR5064 Datasheet - Xilinx

XCR5064 64 Macrocell CPLD with Enhanced Clocking

The XCR5064C CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner™ CPLDs from Xilinx Semiconductors. These devices combine high DS044 (v1.1) February 10, 2000 www.xilinx.com 1-800-255-7778 1 R XCR5064C: 64 Macrocell CPLD with Enhanced Clocking XPLA Architecture Figur.

APPLICATION NOTE 0 R XCR5064C: 64 Macrocell CPLD with Enhanced Clocking 0 14 DS044 (v1.1) February 10, 2000 Product Specification speed and zero power in a 64 macrocell CPLD. With the FZP design technique, the XCR5064C offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique .

XCR5064 Features

* of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is jo

XCR5064 Datasheet (461.14 KB)