XPLA3 - CPLD

Xilinx

Datasheet Details

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Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed Innovative XPLA3 architecture combines high speed with extreme flexibility Based on industry's first TotalCMOS™ PLD - both CMOS design and process technologies Advanced 0.35µ five metal layer E2CMOS process - 1,000 erase/program cycles guaranteed - 20 years data retention guaranteed 3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface - Full Boundary Scan Test.

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Published: Jul 22, 2007 |