SP5610 Datasheet (Zarlink Semiconductor) - 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER

SP5610, 1.3GHz BI-DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER

The SP5610 is programmed from an I2C Bus.

Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format.

The synthesiser can either accept new data (write mode) or send data (read mode).

The LSB of the address byte (R/W) sets the device into write mode if it is low

FEBRUARY 1997 ADVANCE INFORMATION D.S.

3920 3.3 SP5610 1.3GHz BI DIRECTIONAL I2C BUS CONTROLLED SYNTHESISER (Supersedes edition in 1996 Media IC Handbook, HB4599 1.0) The SP5610 is a single chip frequency synthesiser designed for TV tuning systems.

Control data is entered in the standard I2C BUS format.

The device contains 1 addressable current limited output and 4 addressable bi directional open collector ports one of which is a 3 bit ADC.

The information on these ports

SP5610 Features

* J Complete 1.3GHz Single chip System J High Sensitivity RF Inputs J Programmable via I2C Bus J On Chip oscillator with 1kW negative resistance J Low power consumption (5V, 20mA) J Low Radiation J Phase Lock Detector J Varactor Drive Amp Disable J 5 Controllable Outputs J 5 Level ADC J Variable I2C B