SP8402 Datasheet - Zarlink Semiconductor

SP8402 Very Low Phase Noise Divider by 2N

www.DataSheet4U.com SP8402 Very Low Phase Noise Divider by 2N September 2005 The SP8402 is a very low phase noise divider which divides by powers of two. The S0, S1, S2 data inputs select the division ratio in the range 21 to 28. Special circuits techniques have been used to reduce the phase noise considerably below that produced by standard dividers. The data inputs are CMOS or TTL compatible. The SP8402 is packaged in a 28 pin plastic SO package to be compatible with the SP8400 and SP8401 d.

SP8402 Features

* I Very low Phase Noise (Typically -155 to 160dBc/Hz at 1kHz offset) I Supply Voltage 5V N/C N/C N/C VCC +5V GND CLOCK INPUT CLOCK INPUT CLOCK INPUT CLOCK INPUT GND VCC +5V VCC +5V N/C S0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 N/C N/C N/C N/C N/C N/C N/C OUTPUT OUT

SP8402 Datasheet (489.47 KB)