SP8861 Datasheet - Zarlink Semiconductor

SP8861 Low Power Single-Chip Frequency Synthesiser

Prescaler and AM Counter The programmable divider chain is of AM counter design and therefore contains a dual modulus front end prescaler, an A counter which controls the dual modulus ratio and an M counter which controls the bulk multi-modulus division. A programmable divider of this type has a div.

SP8861 1 3GHz Low Power Single-Chip Frequency Synthesiser Supersedes version in the1996 Professional Products IC Handbook, HB2480 - 3.0 DS3640 - 4.0 April 1998 The SP8861 is a low power single chip synthesiser intended for professional radio applications, containing all the elements (apart from the loop amplifier) required to build a PLL frequency synthesis loop The device is serially programmable by a three-wire data highway and contains three independent buffers to store one reference div.

SP8861 Features

* s Improved Digital Phase Detector Eliminates HP28 ‘Dead Band’ Effects s Low Operating Power, Typically 175mW

* FPD and FREF outputs are reversed by the phase detector sense bit in the F1/F2 programming word. The s 1

* 3GHz Operating Frequency above diagram is correct when the sense bit is low.

SP8861_ZarlinkSemiconductor.pdf