A4S12D30FTP Datasheet - Zentel Electronics

A4S12D30FTP 512Mb DDR SDRAM

A4S12D40FTP is a 4-bank x 8,388,608-word x 16-bit, A4S12D30FTP is a 4-bank x 16777216word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output dat.

A4S12D30FTP Features

* -Vdd=Vddq=2.5V+0.2V(G6 Grade) -Vdd=Vddq=2.6V+0.1V(G5 Grade) - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS trans

A4S12D30FTP-ZentelElectronics.pdf