Description
13
Updated FLLEN (FLL enable) bit to be disable by System Reset.Clarified that PortD0/RESET is not a Stop Mode Recovery source.Enhanced UART noise filter description.Corrected Noise Filter Operation figure.Updated USB Bulk Out Transfers Section to include information and a caution regarding USB buffer space accesses.Updated ADC Starting and Stopping Conversions Section.Clarified ADC offset compensation and updated ADC gain compensation formula.Added Development System Overview Section.
Z8F6482-Zilog.pdf
