74AC11074 Datasheet - Texas Instruments

74AC11074 Dual D-Type Positive-Edge-Triggered Flip-Flop

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input that meets the setup-time req.

74AC11074 DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH CLEAR AND PRESET SCAS499A DECEMBER 1986 REVISED APRIL 1996 D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process D 500-mA Typical Latch-Up Immunity at 125°C D Package Options Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N) D, N, OR PW PACKAGE (TOP VIEW) 1PRE 1Q 1Q G.

74AC11074 Datasheet (669.29 KB)