74AC11239 - DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER
The 74AC11239 circuit is designed to be used in high-performance memory-decoding or data- routing applications requiring very short propagation delay times.
In high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories
74AC11239 DUAL 2 LINE TO 4 LINE DECODER/DEMULTIPLEXER Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise t EPIC (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immu
