74F112 Datasheet - Texas Instruments

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

74F112 General Description

The SN74F112 contains two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time require.

74F112 Datasheet (666.05 KB)

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74F112

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Texas Instruments ↗

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666.05 KB

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Dual negative-edge-triggered j-k flip-flop.
SN74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET SDFS048A D2932, MARCH 1987 REVISED OCTOBER 1993

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74F112 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP Texas Instruments

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74F112 General Description

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